Computer Hardware
CPU, Memory, I/O Devices & Storage
CPU Architecture
The brain of the computer — ALU, CU, and Registers
ALU (Arithmetic Logic Unit)
Performs all arithmetic (add, subtract, multiply, divide) and logical (AND, OR, NOT, compare) operations. Results are placed in the Accumulator register.
CU (Control Unit)
Directs all CPU operations: fetches instructions from memory, decodes them, and coordinates the ALU, registers, and buses to execute them. Does not process data itself.
Registers
Tiny, ultra-fast storage locations inside the CPU. Faster than cache or RAM. Hold the current instruction, data being processed, and memory addresses during execution.
Key Registers
| Register | Full Name | Purpose |
|---|---|---|
| ACC | Accumulator | Stores the current result of ALU operations |
| PC | Program Counter | Holds the address of the NEXT instruction to fetch |
| IR | Instruction Register | Holds the CURRENT instruction being decoded/executed |
| MAR | Memory Address Register | Holds the address of the memory location being accessed |
| MBR/MDR | Memory Buffer/Data Register | Temporarily holds data being read from or written to memory |
Word Size: The size of the CPU's registers (8, 16, 32, or 64 bits). A 64-bit processor has 64-bit registers and can address 2⁶⁴ bytes of memory. Larger word size = more data processed per cycle.
Memory Hierarchy
Speed vs capacity trade-off: closer to CPU = faster but smaller
Cache Memory (L1 / L2 / L3)
L1 Cache
Inside CPU core. Fastest, smallest (8–64 KB). Holds current instructions and data.
L2 Cache
On CPU chip, shared between cores. 256 KB – 4 MB. Feeds L1 on cache miss.
L3 Cache
Shared across all cores. 4 MB – 64 MB. Last cache level before RAM. Slowest cache.
Cache hit: Data found in cache → fast retrieval. Cache miss: Data not in cache → fetch from RAM (slower). The CPU's cache controller predicts what data will be needed next.
Primary Memory (RAM & ROM)
| Type | Full Name | Volatile? | Purpose | Subtypes |
|---|---|---|---|---|
| DRAM | Dynamic RAM | Yes (loses data without power) | Main system memory | DDR3, DDR4, DDR5 modules |
| SRAM | Static RAM | Yes | Cache memory (faster than DRAM) | Stays stable without refresh |
| ROM | Read Only Memory | No (permanent) | Stores BIOS/firmware | PROM, EPROM, EEPROM |
| Flash | Flash Memory | No | USB drives, SSDs, memory cards | Combines RAM speed with ROM permanence |
Secondary Storage Devices
Persistent storage — data survives power-off
Hard Disk Drive (HDD)
Magnetic platters spinning at 5400–7200 RPM. Read/write head moves to track data. Cheap and high capacity but slower and fragile.
Capacity: Up to 20 TB · Speed: Slow (ms access)
Solid State Drive (SSD)
Flash memory chips — no moving parts. Much faster than HDD, shock-resistant, silent. More expensive per GB.
Capacity: Up to 8 TB · Speed: Very fast (μs access)
Optical Disk
Laser reads/writes data as pits and lands on a reflective surface. CD (~700 MB), DVD (~4.7 GB), Blu-ray (~25 GB).
Capacity: Up to 128 GB (BD-XL) · Speed: Moderate
Flash / USB Drive
Portable flash memory in USB form factor. Plug and play. Used for data transfer and backup.
Capacity: Up to 2 TB · Speed: Fast (USB 3.0+)
Input Devices
Devices that feed data into the computer
| Device | Type | How It Works | Common Use |
|---|---|---|---|
| Keyboard | Manual key entry | Electrical signal sent per keypress, mapped to ASCII/Unicode | Text and command input |
| Mouse | Pointing device | Optical/laser tracks movement; buttons send click events | GUI navigation, drawing |
| Scanner | Image input | CCD sensor captures light reflected from document | Digitizing documents/photos |
| Barcode Reader | OCR / source data | Laser reads parallel line patterns encoding numbers | Retail, inventory management |
| OMR | Optical Mark Recognition | Detects pencil marks in predefined positions | MCQ answer sheets, surveys |
| OCR | Optical Character Recognition | Software interprets scanned text characters | Converting printed text to editable format |
| MICR | Magnetic Ink Character Recognition | Reads magnetic ink characters on cheques | Bank cheque processing |
| Webcam / Digital Camera | Image/video input | CCD/CMOS sensor converts light to digital signal | Video calls, photography |
| Microphone | Audio input | Converts sound waves to electrical signal | Voice input, recording |
| Touchscreen | Touch/gesture input | Capacitive or resistive layer detects touch coordinates | Smartphones, kiosks, tablets |
Output Devices
Devices that present processed results to the user
Monitor (VDU)
Visual (Soft Copy)
Displays output on screen. Types: LCD, LED, OLED. Resolution: 1080p, 4K. Measured in inches diagonally.
Printer
Hard Copy
Produces permanent paper output. Types: Inkjet (home), Laser (office), Dot-matrix (continuous paper), Thermal (receipts).
Plotter
Hard Copy (large)
Produces high-precision large-format drawings. Used by engineers, architects, cartographers.
Speakers
Audio output
Convert digital audio signal to sound waves. Used in multimedia, voice responses, alarm systems.
Projector
Visual (large scale)
Projects display onto a large screen or wall. Used in classrooms, conferences, cinemas.
Headphones
Personal audio
Private audio output. Used in recording studios, gaming, assistive hearing devices.
Bus Architecture & Instruction Cycle
How data travels and how instructions execute
System Bus Types
Data Bus
Carries actual data between CPU, memory, and I/O devices. Width = word size (8/16/32/64 bits). Bidirectional.
Address Bus
Carries memory addresses from CPU to memory. Width determines how much memory CPU can address. Unidirectional.
Control Bus
Carries control signals: read/write commands, interrupt requests, clock signals. Coordinates all components.
Instruction Cycle (Fetch → Decode → Execute → Store)
1. FETCH
PC → MAR; Memory sends instruction → MBR → IR; PC increments
2. DECODE
CU reads IR; identifies opcode (what to do) and operand (what to do it to)
3. EXECUTE
ALU performs the operation; result stored in ACC register
4. STORE
Result written back to memory or I/O device if required
RISC vs CISC
Two philosophies for CPU instruction set design
| Feature | RISC | CISC |
|---|---|---|
| Full Name | Reduced Instruction Set Computer | Complex Instruction Set Computer |
| Instructions | Small, simple, fixed-size | Large, complex, variable-size |
| Execution | Each instruction: 1 clock cycle | Some instructions: many clock cycles |
| Registers | Many general-purpose registers | Fewer registers |
| Memory access | Load/Store model only | Instructions can directly access memory |
| Compiler | Complex compiler needed | Simpler compiler |
| Examples | ARM (mobile), MIPS, PowerPC | Intel x86, AMD (PCs, laptops) |
Why RISC won in mobile
ARM (RISC) chips dominate smartphones because simple instructions = less transistors = less heat = less battery. Every iPhone and Android phone uses ARM.
Why CISC stays in PCs
x86 instruction set compatibility spans 40+ years. Your modern Intel/AMD CPU has a CISC front-end that internally translates to RISC micro-operations.
Analytical Questions
Unit 2 Summary
Core topics and important exam questions
Core Topics Covered
CPU components: ALU, CU, Registers
Key registers: PC, ACC, IR, MAR, MBR
Memory hierarchy (registers → cache → RAM → secondary)
Primary memory: RAM (DRAM, SRAM), ROM, Flash
Secondary storage: HDD, SSD, optical, USB
Input devices (keyboard, mouse, scanner, OMR, MICR)
Output devices (monitor, printer, projector)
System bus: data, address, control
Instruction cycle: Fetch → Decode → Execute → Store
RISC vs CISC comparison
Important Exam Questions
Explain the components of CPU with diagram. (5 marks)
Describe the memory hierarchy. Why is cache needed? (5 marks)
Compare RAM and ROM. Compare HDD and SSD. (5 marks)
Explain the fetch-decode-execute cycle. (5 marks)
Differentiate between RISC and CISC with examples. (5 marks)
List and explain common input and output devices. (5 marks)
Syllabus Coverage Checklist
Motherboard
CPU architecture (ALU, CU, registers)
Memory hierarchy and types
Storage devices
Ports and interfaces
Expansion slots
Input/output hardware
BIOS/CMOS/SMPS (see Unit 1 for motherboard detail)
Microprocessor basics
How to Remember This Unit
Mnemonics for hardware components
CPU = "ACE"
A=ALU (does arithmetic) · C=Control Unit (directs traffic) · E=... well, registers (inside everywhere)
Memory hierarchy: "R-Can-Ruin-a-Superfast-System"
R=Registers · Ca=Cache · Ra=RAM · S=Secondary storage
Registers: "PC Always Installs Missed Data"
PC=Program Counter · ACC=Accumulator · IR=Instruction Register · MAR=Memory Address Register · MBR=Memory Buffer Register
RISC = "SAFE"
S=Simple instructions · A=ARM architecture · F=Fixed size · E=Each instruction = 1 cycle
Bus types: "DAC"
D=Data bus (carries data) · A=Address bus (carries addresses) · C=Control bus (carries commands)
Instruction cycle: "FDES"
F=Fetch · D=Decode · E=Execute · S=Store
Unit 2 Quiz
1. The part of the CPU that performs arithmetic and logical operations is called:
2. Which register holds the memory address of the next instruction to be fetched?
3. Cache memory is placed between:
4. Which is the correct order of memory speed (fastest to slowest)?
5. RISC architecture is characterized by: