Sequential Logic Circuits
12h
Class hours
6
Topics
0%
0/32 done
Why This Unit Matters
Memory-bearing circuits where outputs depend on current inputs AND past state — latches, flip-flops, registers, and state machines.
Why This Unit Matters
Unit 4 is where digital circuits gain memory and intelligence. Every computer, phone, and microcontroller relies on sequential logic — flip-flops store data in registers, state machines implement protocols and controllers, and shift registers move data in and out of processors. The JK flip-flop appears in TU BCA exams every single year, and state machine design is a guaranteed Group C (10-mark) question.
Unit Overview in Simple Words
Memory Elements
Latches and flip-flops — the hardware that remembers one bit of information.
Clocked Storage
Edge-triggered flip-flops — SR, D, JK, T — each with unique behavior.
Shift Registers
Four modes of shift registers — serial/parallel I/O for data movement.
State Machines
Moore and Mealy machines — designing circuits that respond to sequences.
Learning Outcomes
Teaching Hours
12 hours
Topics
6 main topics
Exam Weight
~25% of paper
Must Know
JK FF + FF Conversion + State Machine
Introduction to Sequential Logic
Definition
A sequential circuit is a digital circuit whose output depends not only on the present inputs but also on the past history of inputs (i.e., the current state). It has memory — it remembers what happened before.
Formula: Output = f(Present State, Input) and Next State = g(Present State, Input)
Has Memory
Stores the past state using flip-flops or latches. Output depends on history.
Clock-Driven
State changes happen at specific clock moments — synchronous circuits are predictable and reliable.
Feedback Present
The output feeds back as input — the 'next state' becomes the 'present state' on the next clock edge.
State Machine
Every sequential circuit can be described as a finite state machine with states and transitions.
Sequential vs Combinational
| Feature | Combinational | Sequential |
|---|---|---|
| Memory | No memory | Has memory (flip-flops) |
| Output depends on | Present inputs only | Present inputs + past state |
| Clock required | No | Usually yes (synchronous) |
| Feedback | No feedback paths | Output fed back as state |
| State concept | No states | Has finite number of states |
| Examples | Adder, MUX, Decoder | Flip-flop, Counter, Register |
| Analysis tool | Truth Table / K-map | State Diagram / State Table |
The Concept of State
A state is a snapshot of all memory in the circuit at a given moment. It summarizes the entire past history of inputs that is needed to predict future outputs.
State Terminology
State Transition Flow
The Next State feeds back to become the Present State on each clock tick — this is what creates "memory."
Clock Signal
The clock is a periodic signal that alternates between 0 and 1. It controls when state changes happen in synchronous sequential circuits. Without a clock, circuits would race — outputs would change unpredictably.
Clock Waveform
Triggering and Its Types
Triggering determines exactly when a flip-flop or latch responds to its inputs and changes state. Different triggering methods affect timing, race conditions, and circuit design.
Active whenever the enable/clock is at a fixed level (HIGH or LOW). A HIGH level-triggered latch is transparent when clock=1 — changes in input immediately change output. Problem: multiple state changes can occur in one clock cycle (timing hazards).
Flip-flop captures input and updates output ONLY on the rising edge (0→1 transition) of the clock. All other times, input changes are ignored. Most common for synchronous design. Clear and predictable.
Flip-flop captures input and updates output ONLY on the falling edge (1→0 transition) of the clock. Denoted with a small bubble or ▽ on clock input in logic diagrams. Used when falling-edge timing is more convenient.
A two-stage FF: master captures input on rising edge (clock=1), slave transfers to output on falling edge (clock=0). Eliminates 1s-catching problem of simple edge triggering. Used in the classic Master-Slave JK flip-flop.
| Trigger Type | Active When | Latch or FF | Problem |
|---|---|---|---|
| Level HIGH | Clock = 1 | Latch | Multiple transitions per cycle |
| Level LOW | Clock = 0 | Latch | Multiple transitions per cycle |
| Positive Edge | 0 → 1 transition | Flip-Flop | None (most common) |
| Negative Edge | 1 → 0 transition | Flip-Flop | None |
| Pulse (Master-Slave) | Entire HIGH pulse | Flip-Flop | 1s-catching in SR type |
Synchronous vs Asynchronous Sequential Circuits
Synchronous
- All flip-flops share a common clock signal
- State changes only at clock edges
- Easier to design and analyze
- Timing is predictable — no race conditions
- Almost all modern digital systems are synchronous
- Example: Registers, synchronous counters
Asynchronous
- No common clock — state changes when inputs change
- Faster (no clock delay), but harder to design
- Prone to race conditions and hazards
- Each FF may have different propagation delays
- Example: Ripple counters, SR latches
Latches & Flip-Flops
SR Latch
The SR Latch (Set-Reset Latch) is the fundamental memory element. It stores 1 bit and has two stable states. Built from two cross-coupled gates (NOR or NAND). It is level-sensitive — it responds whenever its inputs change (no clock).
S = 1, R = 0 → Q = 1 (Set)
S = 0, R = 1 → Q = 0 (Reset)
S = 0, R = 0 → Q unchanged (Remember)
S = 1, R = 1 → Both outputs = 0 (INVALID — forbidden state)
| S | R | Q (next) | Action |
|---|---|---|---|
| 0 | 0 | Q (no change) | Hold / Remember |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Invalid | ⚠ Forbidden |
NOR-based SR Latch. Both Q and Q' become 0 when S=R=1 (violates complement rule).
D Latch (Transparent Latch)
The D Latch eliminates the forbidden state of the SR latch by tying R = S' (complement of S). It has one data input D and one enable input E (or EN). Called "transparent" because when E = 1, Q follows D immediately.
| E (Enable) | D | Q (next) | Action |
|---|---|---|---|
| 0 | X | Q (no change) | Latch closed — stores value |
| 1 | 0 | 0 | Q follows D = 0 |
| 1 | 1 | 1 | Q follows D = 1 |
X = don't care. D latch has no forbidden state — much safer than SR.
Boolean Expression
Q⁺ = D (when E = 1) | Q⁺ = Q (when E = 0)
Why use it: The D latch is the building block for registers and memory cells. When E = 0, it stores its value indefinitely (until E goes high again).
Problem: If the enable stays high for a long time and D changes multiple times, all changes propagate through — not always desirable. Solution: use edge-triggered D flip-flop.
Latch vs Flip-Flop
| Feature | Latch | Flip-Flop |
|---|---|---|
| Triggering | Level-sensitive (EN signal) | Edge-triggered (clock edge) |
| When it changes | Whenever enable is active | Only at clock edge |
| Clock needed | No (has enable instead) | Yes |
| Speed | Faster (propagates instantly) | Controlled by clock |
| Hazard risk | Higher (glitches propagate) | Lower (captured at edge) |
| Use in sync design | Avoid in synchronous systems | Standard element |
| Common types | SR Latch, D Latch | SR, D, JK, T flip-flops |
| Symbol | Triangle or EN pin | Triangle with clock triangle |
SR Flip-Flop
An SR flip-flop behaves like an SR latch but with edge-triggered input. It captures S and R only at the active clock edge and ignores changes at other times.
| S | R | Q⁺ (next state) | Operation |
|---|---|---|---|
| 0 | 0 | Q | No change (hold) |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ? | Undefined (forbidden) |
Characteristic table: given present S, R, what is next Q?
Characteristic Equation
Q⁺ = S + R'Q (SR = 0 constraint)
Excitation Table
| Q (present) | Q⁺ (next) | S | R |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | X | 0 |
X = don't care (either 0 or 1 gives same result)
The excitation table asks: "What inputs do I need to achieve a desired state transition?" This is the reverse of the characteristic table — used in sequential circuit design.
D Flip-Flop (Data / Delay)
The D flip-flop is the most widely used FF in digital systems. It has a single data input D. On each clock edge, Q captures whatever D was. It effectively delays D by one clock cycle.
| D | Q⁺ (next state) | Operation |
|---|---|---|
| 0 | 0 | Reset |
| 1 | 1 | Set |
Simplest characteristic table — Q just follows D with one clock delay.
Characteristic Equation
Q⁺ = D
Uses:
- Shift registers (D FF chains)
- Pipeline registers in CPUs
- Bounce elimination (for switch inputs)
- Data synchronization between clock domains
JK Flip-Flop ⭐ (Most Important)
The JK flip-flop improves on SR by eliminating the forbidden state. When J = K = 1, instead of being undefined, the output toggles (Q becomes Q'). J stands for "Jump" (Set) and K stands for "Kill" (Reset).
| J | K | Q⁺ (next state) | Operation |
|---|---|---|---|
| 0 | 0 | Q | No change |
| 0 | 1 | 0 | Reset (Kill) |
| 1 | 0 | 1 | Set (Jump) |
| 1 | 1 | Q' | Toggle ← key feature |
No forbidden state — J=K=1 gives toggle, not undefined output.
Characteristic Equation
Q⁺ = JQ' + K'Q
Excitation Table
| Q (present) | Q⁺ (next) | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
X = don't care. JK has the most X entries → easiest K-map minimization
JK has the most X (don't care) entries → simplest K-map minimization → preferred in sequential circuit design problems.
T Flip-Flop (Toggle)
The T flip-flop is a simplified JK with J and K tied together. When T = 0, hold. When T = 1, toggle. Essential for counter design.
| T | Q⁺ (next state) | Operation |
|---|---|---|
| 0 | Q | Hold (no change) |
| 1 | Q' | Toggle |
Derived from JK by connecting J = K = T.
Characteristic Equation
Q⁺ = T ⊕ Q (XOR)
Derived from JK with J=K=T
Q⁺ = TQ' + T'Q = T ⊕ Q
Master-Slave JK Flip-Flop
The Master-Slave JK consists of two latches in series. The master captures input during clock HIGH; the slave transfers to output during clock LOW. This ensures the output changes only once per clock cycle, fixing the race-around problem.
Operation Sequence
CLK = 1 (Master active)
Master JK latch captures J, K inputs. Output of master changes. Slave is disabled (CLK=0 for slave because of inverter).
CLK ↓ (Falling edge)
Master gets disabled. Slave gets enabled. Slave's output (Q, Q') changes to match master's stored value.
CLK = 0 (Slave active)
Slave holds the value captured at falling edge. Master is isolated — J,K changes don't affect anything.
Flip-Flop Comparison Summary
| FF Type | Inputs | Char. Equation | Toggle? | Forbidden? | Best Use |
|---|---|---|---|---|---|
| SR | S, R | S + R'Q | No | Yes (SR=11) | Simple set/reset control |
| D | D | D | No | No | Registers, pipelines |
| JK | J, K | JQ' + K'Q | Yes (J=K=1) | No | General purpose, design problems |
| T | T | T ⊕ Q | Always (T=1) | No | Counters, frequency dividers |
Interactive Flip-Flop Simulator
Set inputs and pulse the clock to observe state changes.
1. Set Inputs
2. Current State Q(t)
0Transition History
No clock pulses yet. Pulse the clock to see transitions.
Excitation Tables
Excitation tables are the key to designing sequential circuits. They tell you: "What inputs do I need to move from Q to Q+?"
| Q (present) | Q⁺ (next) | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
X = don't care. JK has the most X entries → easiest K-map minimization
Flip-Flop Conversions
What is FF Conversion?
Sometimes you have one type of flip-flop available but need to implement another type's behavior. FF conversion means designing combinational logic circuits to place between the available FF's inputs and the desired FF's inputs, so that the available FF behaves exactly like the target FF.
Standard 5-Step Conversion Procedure
Write the characteristic table of the target (desired) FF
List all combinations of current state Q and desired next state Q⁺. This defines what transitions we need to achieve.
Write the excitation table of the available (given) FF
For each (Q → Q⁺) transition, look up what inputs the available FF needs. Fill in the required inputs (use don't cares X where applicable).
Form the combined conversion table
Merge: columns = [current inputs of target FF, Q, Q⁺, required inputs of available FF]. Each row represents one truth table entry.
Draw K-maps for each input of the available FF
Variables: inputs of target FF + current state Q. Minimize each K-map to get the Boolean expression.
Implement the resulting expressions with gates
Connect the gate circuit's outputs to the available FF's inputs. The available FF now behaves like the target FF.
Convert JK Flip-Flop to D Flip-Flop
We have a JK FF and want it to behave as a D FF. We need to find: J = f(D, Q) and K = f(D, Q).
| D (target input) | Q (present) | Q⁺ (next) | J (required) | K (required) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X |
| 0 | 1 | 0 | X | 1 |
| 1 | 0 | 1 | 1 | X |
| 1 | 1 | 1 | X | 0 |
Q⁺ = D (target). J,K from JK excitation table for each Q→Q⁺ transition.
K-map for J
| Q=0 | Q=1 | |
|---|---|---|
| D=0 | 0 | X |
| D=1 | 1 | X |
Simplified expression
J = D
K-map for K
| Q=0 | Q=1 | |
|---|---|---|
| D=0 | X | 1 |
| D=1 | X | 0 |
Simplified expression
K = D'
Result
J input circuit
J = D
K input circuit
K = D' (NOT gate on D)
Connect D directly to J, and D through a NOT gate to K. When D=0: J=0, K=1 → Reset (Q→0). When D=1: J=1, K=0 → Set (Q→1). JK now behaves exactly like D FF.
Registers
Definition
A register is a group of flip-flops used to store a multi-bit binary number. An n-bit register consists of n flip-flops and can store n bits simultaneously. Registers are the basic storage elements inside a CPU — the "registers" in assembly language (AX, BX, etc.) are hardware shift registers made of D flip-flops.
Serial In Serial Out
Data enters one bit at a time from one end and exits one bit at a time from the other. Simplest shift register. Acts as a delay line — introduces n-clock-cycle delay.
Serial In Parallel Out
Data enters bit by bit, all n bits available simultaneously at output after n clock cycles. Used in serial-to-parallel conversion (e.g., receiving serial data from UART).
Parallel In Serial Out
All n bits loaded simultaneously (parallel load), then shifted out one bit at a time per clock. Used in parallel-to-serial conversion (e.g., transmitting parallel data serially).
Parallel In Parallel Out
All n bits loaded simultaneously, all n bits available simultaneously at output. Fastest mode — one clock cycle for load and read. Used as CPU accumulators.
SISO — Serial In, Serial Out
Each D flip-flop passes its output to the next FF's input. On each clock edge, every bit shifts right by one position.
Example: Load 1011 serially (MSB first), read serially after 4 clocks.
Operation
SISO function
Serial delay line: n clock cycles to pass through n-bit data
SIPO — Serial In, Parallel Out
Same hardware as SISO — the only difference is that outputs of all flip-flops are connected to external wires. After clocking in n bits, all bits are available simultaneously as Q₀, Q₁, Q₂, Q₃.
Serial → Parallel conversion example
Input serial data: 1 → 1 → 0 → 1 (4 clock cycles, MSB first)
After CLK4, parallel outputs: Q₀=1, Q₁=1, Q₂=0, Q₃=1 → reads 1101
Applications
- UART (Universal Async Receiver Transmitter) — serial data → parallel bus
- SPI/I2C interfaces — receiving serial sensor data
- Barcode scanner input decoding
- RS-232 serial communication → parallel computer bus
PISO — Parallel In, Serial Out
PISO has two modes: load mode (parallel data loaded in one clock cycle) and shift mode (data shifted out one bit per clock cycle). A mode-select signal (LOAD/SHIFT) controls which operation occurs.
PISO operation sequence
Application: Parallel-to-serial conversion for transmission over single wire (USB, Ethernet frame building).
PIPO — Parallel In, Parallel Out
The fastest register — all bits loaded and read in a single clock cycle. Used in CPU accumulators, temporary storage registers, and buffers in digital systems.
How it works
- All D inputs connected to parallel data lines
- Single clock edge loads all bits simultaneously
- All Q outputs available simultaneously
- No shifting — pure storage register
- Can include synchronous clear/reset
Uses in real systems
- CPU general-purpose registers (AX, BX, SP)
- Instruction register (holds current instruction)
- Memory Address Register (MAR)
- Memory Buffer Register (MBR)
- Program Counter (PC) — actually a PIPO with increment logic
Bidirectional Shift Register
A bidirectional shift register can shift data both left and right, controlled by a direction select bit. Uses 2:1 multiplexers at each FF input to choose between left-shift and right-shift data paths.
Operation modes
| S₁ | S₀ | Mode | Description |
|---|---|---|---|
| 0 | 0 | Hold | No change — present state maintained |
| 0 | 1 | Shift Right | Data shifts right; serial input enters from left |
| 1 | 0 | Shift Left | Data shifts left; serial input enters from right |
| 1 | 1 | Parallel Load | All bits loaded simultaneously from parallel inputs |
Application: Arithmetic shift operations (multiply/divide by 2), serial communication that must handle both directions, and universal shift register ICs (e.g., 74194).
Interactive 4-Bit Shift Register
Apply clock pulses to see data shift through the registers.
Register Types — Summary Table
| Type | Input | Output | Clocks to Load | Clocks to Read | Speed | Application |
|---|---|---|---|---|---|---|
| SISO | Serial | Serial | n | n | Slow | Delay line |
| SIPO | Serial | Parallel | n | 1 | Medium | Serial → Parallel |
| PISO | Parallel | Serial | 1 | n | Medium | Parallel → Serial |
| PIPO | Parallel | Parallel | 1 | 1 | Fast | CPU registers |
| Bidirectional | Parallel/Serial | Parallel/Serial | 1 or n | 1 or n | Flexible | Arithmetic shift |
State Machines (Moore & Mealy)
Moore Machine
Output depends only on present state
Named after Edward F. Moore. The output is a function of the current state only. Output is labeled inside each state circle in the state diagram.
Output equation
Z = f(Q) — state only
- Output changes only at clock edges (stable output)
- Generally requires more states than Mealy
- Easier to analyze and debug
- Output labeled: state circle shows "State / Output"
Mealy Machine
Output depends on state AND current input
Named after George H. Mealy. The output is a function of both the current state and the input. Output is labeled on the transition arc in the state diagram.
Output equation
Z = f(Q, X) — state + input
- Output can change immediately when input changes (reactive)
- Fewer states needed than Moore for same function
- Output labeled on arc: "Input / Output"
- Potential glitches if input is noisy
Interactive Sequence Detector
Moore Machine detecting "101" (Overlapping).
| Feature | Moore | Mealy |
|---|---|---|
| Output depends on | Present state only | Present state + input |
| Output labeled in diagram | Inside state circles | On transition arcs |
| Number of states | More states needed | Fewer states needed |
| Output timing | Changes at clock edge | Can change anytime (async) |
| Glitch risk | Low (synchronized) | Higher (input-dependent) |
| Synchronous output | Yes | Not guaranteed |
| Preferred when | Output stability needed | Fewer states is priority |
State Table
A state table (also called transition table) is the tabular form of the state diagram. It lists every combination of present state and input, showing the next state and output.
Moore Machine State Table (Detect single 1)
| Present State | Input X=0 | Input X=1 | Output Z |
|---|---|---|---|
| S0 | S0 | S1 | 0 |
| S1 | S0 | S1 | 1 |
Output Z is listed as a separate column — depends only on state.
Mealy Machine State Table (Detect consecutive 1s)
| Present State | X=0 (NS/Z) | X=1 (NS/Z) |
|---|---|---|
| S0 | S0 / 0 | S1 / 0 |
| S1 | S0 / 0 | S1 / 1 |
Output is shown with NS: "Next State / Output". Z=1 when consecutive 1 detected.
State Reduction Technique
State reduction minimizes the number of states in a state machine without changing its input-output behavior. Fewer states → fewer flip-flops → simpler circuit.
Method: Equivalent State Identification
Two states Si and Sj are equivalent if and only if:
If both conditions hold, merge the equivalent states — replace all occurrences of one with the other. Repeat until no further reduction is possible.
State Reduction — Step Through
Step 1 of 4Original State Table (with redundant states)
We have 4 states. Check for states with identical next-state and output behavior.
| State | Input=0 (NS, Out) | Input=1 (NS, Out) |
|---|---|---|
| S0 | S0, 0 | S1, 0 |
| S1 | S0, 0 | S2, 0 |
| S2 | S0, 0 | S1, 0 |
| S3 | S0, 0 | S2, 0 |
Sequential Circuit Design Procedure
Understand the problem
Identify the number of inputs, outputs, and describe the behavior for every input sequence. Determine Moore or Mealy.
Draw state diagram
Create circles (states) and directed arcs (transitions with input/output labels). Start from the initial state.
Reduce states (optional)
Apply state equivalence reduction to minimize the number of states.
State assignment
Assign binary codes to each state. For n states, need ⌈log₂n⌉ flip-flops. Choose state codes to minimize combinational logic.
Write the state table
Fill in present state (PS), input (X), next state (NS), and output (Z) for all combinations.
Choose flip-flop type
Select FF type (usually JK or D). Write the excitation table for the chosen FF.
Derive FF input equations
For each FF input, use K-map with variables (state bits + inputs) to find minimized Boolean expressions.
Implement the circuit
Draw the combinational logic (from input equations) feeding the FF inputs. Add output logic. Verify with timing simulation.
Worked Example: "11" Sequence Detector
We need to remember how many consecutive 1s we've seen. Three states suffice:
Transitions:
S0 + X=0 → S0 (stay, saw 0)
S0 + X=1 → S1 (one 1 seen)
S1 + X=0 → S0 (streak broken)
S1 + X=1 → S2 (two consecutive 1s!)
S2 + X=0 → S0 (streak broken)
S2 + X=1 → S2 (still in ≥2 consecutive 1s)
Sequence Detector Demo
Enter bits one at a time. Output = 1 when pattern detected.
Practice & Self-Assessment
Quick Recall
Try to answer from memory. Click to reveal.
TU BCA Exam-Style Questions
Draw and explain the JK Master-Slave flip-flop. How does it solve the race-around condition?
Convert a JK flip-flop to behave as a D flip-flop. Show the K-map and derivation.
Design a sequence detector for the pattern '101' using a Moore machine.
What are the types of shift registers? Explain PISO with a diagram and operation table.
Differentiate between synchronous and asynchronous sequential circuits.
Mini-Test (8 Questions)
Test yourself! All questions to submit.
Q1.Which flip-flop eliminates the forbidden state of SR by allowing toggle?
Q2.The characteristic equation of a JK flip-flop is:
Q3.In a D flip-flop, what is Q⁺ (next state)?
Q4.A Master-Slave JK flip-flop changes its output on:
Q5.The race-around condition occurs in JK flip-flop when:
Q6.Which register type performs serial-to-parallel conversion?
Q7.In a Moore machine, the output depends on:
Q8.To convert JK to T flip-flop, the connections are:
How to Remember Unit 4
Memory Tricks for Unit 4
FF Names — What the Letters Mean
SR = Set/Reset. D = Data (or Delay — it delays by 1 clock). J = Jump (like Set), K = Kill (like Reset). T = Toggle (flips every time T=1).
JK Characteristic: NCRT
When J=K: NC (No Change if 00), Reset (01), Toggle... wait no. Order: No Change, Kill, Jump, Toggle. Think 'No Change – Reset – Set – Toggle' for JK=00,01,10,11.
D FF: Simplest of all
D flip-flop is so simple: Q⁺ = D. Period. No other variables. It just copies D on the clock edge. 'D' stands for Data — it stores whatever data you give it.
T FF: Think XOR
T flip-flop equation is Q⁺ = T XOR Q. Remember: XOR means 'different = 1'. When T=1, Q⁺ is different from Q (it toggles). When T=0, Q⁺ same as Q (no change).
Excitation Table X Entries Rule
More X entries = less hardware needed in K-maps. JK has MOST X entries → best for design problems. SR has X entries but also a forbidden state. D and T have NO X entries — deterministic.
Register SIPO vs PISO: Serial in/out is SLOW
SIPO: Serial enters (slow), Parallel exits (fast, all at once). PISO: Parallel enters (fast), Serial exits (slow). When SERIAL is the INPUT, you wait n clocks to load. When SERIAL is the OUTPUT, you need n clocks to read all bits.
Moore vs Mealy: WHERE is the output?
MoORe = Output in the ciRcle (state). MeaLy = output on the Line (arc/transition). Mealy has fewer states because one state can give multiple outputs. Moore is more stable (output only changes with state).
Master-Slave: Master TAKES, Slave GIVES
Master takes/captures input during CLK=1 (master is active, slave is locked). Slave gives/shows output during CLK=0 (slave is active, master is locked). Output only appears when clock falls.
Flip-Flop Master Cheat Sheet
| FF | Inputs | Q⁺ (char. eq) | Excitation key rule | Forbidden? | Toggle? | Best for |
|---|---|---|---|---|---|---|
| SR | S, R | S + R'Q | 0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0 | ⚠ Yes | — | Basic. Avoid SR=11 |
| D | D | D | D = Q⁺ (always equal) | ✓ No | — | Simplest. Registers |
| JK | J, K | JQ' + K'Q | Most X entries → easy K-maps | ✓ No | ✓ Yes | General purpose. Best for design |
| T | T | T ⊕ Q | T = Q ⊕ Q⁺ (T=1 when change needed) | ✓ No | ✓ Yes | Counters. Derived from JK |
FF Conversion Quick Reference
J = D, K = D'
J = T, K = T
J = S, K = R
D = JQ' + K'Q
D = T ⊕ Q
T = JQ' + KQ
S = D, R = D'
T = D ⊕ Q
Register Types — Remember This Grid
PIPO
Fastest: 1 CLK in, 1 CLK out
CPU registers
PISO
Load 1 CLK, output n CLKs
Parallel→Serial
SIPO
Input n CLKs, output 1 CLK
Serial→Parallel
SISO
Slowest: n CLKs in, n CLKs out
Delay line
Memory anchor: First letter = INPUT type (P=Parallel, S=Serial), second letter = OUTPUT type. PIPO has the most P's → most parallel → fastest. SISO has the most S's → all serial → slowest.