Unit 5: Counters & Registers | Digital Logic

5Unit 5

Counters & Shift Registers

Class hours

Topics

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Why This Unit Matters

Circuits that count pulses and shift data — essential building blocks for timing, sequencing, and data communication systems.

Why This Unit Matters

Unit 5 closes the loop — counters and shift registers are the circuits that make sequential systems do things over time. Every digital clock, timer, communication interface, and CPU uses these circuits. The ripple counter timing diagram appears in TU BCA exams almost every year, and ring/Johnson counter comparison is a popular Group B question. Mastering this unit completes your understanding of the entire digital logic stack.

Unit Overview

Ripple Counters

Simplest counter — chain of T FFs. MOD-N design with NAND reset feedback.

Sync Counters

All FFs share one clock. Faster, glitch-free. Systematic AND gate design.

Special Counters

Ring, Johnson, BCD, Gray — each optimized for a specific pattern or application.

Shift Registers

SISO/SIPO/PISO/PIPO and universal 74194 — moving data through FFs.

Learning Outcomes

1Draw and analyze 4-bit ripple counter circuit and timing diagram with propagation delay

2Design MOD-5, MOD-7, MOD-10, MOD-11 ripple counters using NAND feedback

3Compare synchronous and asynchronous counters; explain advantage of synchronous design

4Derive JK input equations for synchronous counters using excitation tables and K-maps

5Design synchronous MOD-6 counter completely from scratch

6Draw and explain ring counter, Johnson counter, and BCD decade counter

7Compare ring vs Johnson counter — state count, feedback, encoding

8Explain Gray code counter and its glitch-free property

9Explain all 4 shift register modes (SISO/SIPO/PISO/PIPO) with circuits and applications

10Describe 74194 universal shift register and its 4 operating modes

⏱️

Teaching Hours

8 hours

📌

Topics

5 main topics

🎯

Exam Weight

~20% of paper

⚠️

Must Know

Ripple counter timing + Ring/Johnson + MOD-N design

Asynchronous (Ripple) Counters

Definition

An asynchronous (ripple) counter is a sequential circuit that counts clock pulses. It is called "ripple" because the clock signal is applied only to the first flip-flop — subsequent FFs are clocked by the output of the previous FF. State changes ripple through the chain like a wave.

⏱️

3-Bit Up Counter (Mod-8)

Watch the difference between synchronous parallel updates and asynchronous ripple delays.

FF2

Main CLK

FF1

Main CLK

FF0

Main CLK

State Q₂Q₁Q₀000

Decimal0

Clock Pulses0

🌊

Ripple Effect

Clock applied only to FF0. Each subsequent FF triggered by Q' of the previous one.

⚡

Delay Accumulation

Propagation delay accumulates across FFs. For n FFs, worst-case delay = n × tpd.

📉

Simple but Slow

Simple to build — fewer connections. But slower than synchronous. Prone to glitches during transitions.

2-bit Ripple Counter (MOD-4)

Two T flip-flops with T=1 (always toggle). FF0 clocked by CLK, FF1 clocked by Q0' (complement of FF0). Counts: 00 → 01 → 10 → 11 → 00 (repeats — 4 states, so MOD-4).

State Sequence

Clock	Q1	Q0	Decimal
0 (start)	0	0	0
1	0	1	1
2	1	0	2
3	1	1	3
4 (reset)	0	0	0

2-bit Ripple Counter Demo

MOD-4

Q20

Q10

Q00

decimal

Q0 toggles every clock. Q1 toggles every 2 clocks.

4-bit Ripple Counter (MOD-16)

Four T flip-flops in a chain. Counts 0–15 (16 states = MOD-16). Each FF output frequency is half the frequency of the previous one — a natural frequency divider.

Fig 5.1 — Four T flip-flops in chain; each FF clocked by Q' of the previous FF

Fig 5.2 — Q0 toggles every CLK edge, Q3 (MSB) is the slowest changing output

Notice: Q0 toggles every CLK, Q1 every 2 CLKs, Q2 every 4 CLKs, Q3 every 8 CLKs. Each stage divides frequency by 2.

Up/Down Ripple Counter

An up counter uses Q' (complement) of each FF to clock the next FF. A down counter uses Q (true output) to clock the next FF — this reverses the counting direction. An up/down counter uses a MUX or AND-OR logic to select between Q and Q' based on an UP/DOWN control signal.

Up Counter

FF(i+1) clocked by Q(i)' (complement) of previous FF
Counts 0, 1, 2, 3, ... up to 2ⁿ-1, then wraps to 0
Each FF toggles when the previous FF transitions from 1 → 0

Clock connection

CLK(i+1) = Q(i)' = complement of Q(i)

Down Counter

FF(i+1) clocked by Q(i) (true output) of previous FF
Counts 2ⁿ-1, 2ⁿ-2, ..., 1, 0, then wraps back
Each FF toggles when the previous FF transitions from 0 → 1

Clock connection

CLK(i+1) = Q(i) = true output of Q(i)

Timing Diagram Analysis & Propagation Delay

The key disadvantage of ripple counters is cumulative propagation delay. If each FF has a propagation delay of t_pd, then after n clock stages, the last FF's output changes only after n×t_pd from the original clock edge.

Propagation Delay Problem

FF0 changes after:1 × tpd from clock edge

FF1 changes after:2 × tpd from clock edge

FF2 changes after:3 × tpd from clock edge

FF3 (MSB) changes after:4 × tpd — WORST CASE for 4-bit counter

Glitch effect: During the transition from 0111 (7) to 1000 (8), the counter momentarily passes through 0110, 0100, 0000 before settling at 1000. These spurious states can trigger incorrect circuit behavior downstream.

Maximum clock frequency

f_max = 1 / (n × tpd + setup_time)

MOD-N Counters (Truncated Ripple Counters)

A MOD-N counter counts from 0 to N-1 (N states total), then resets to 0. To build a ripple MOD-N counter: use enough FFs to count beyond N, then detect the count N using a NAND gate and immediately clear all FFs to 0.

General Design Method

1Determine how many FFs needed: use n FFs where 2ⁿ ≥ N.

2Identify binary code of N (the count that triggers reset): this is the NAND gate input.

3Connect the NAND gate: inputs = all Q bits that are 1 in the binary representation of N.

4NAND output → CLR (clear) inputs of all FFs. When count = N, all bits matching N go HIGH → NAND output goes LOW → CLR = 0 → all FFs reset to 0.

5Counter skips state N (it's so brief it often can't be seen) and resumes from 0.

MOD	Count range	Reset on	Binary of reset	NAND inputs	FFs needed
MOD-5	0 – 4	5	0101	Q2, Q0	3
MOD-6	0 – 5	6	0110	Q2, Q1	3
MOD-7	0 – 6	7	0111	Q2, Q1, Q0	3
MOD-10	0 – 9	10	1010	Q3, Q1	4
MOD-11	0 – 10	11	1011	Q3, Q1, Q0	4
MOD-12	0 – 11	12	1100	Q3, Q2	4

MOD-10 (Decade) Counter

MOD-10

Q30

Q20

Q10

Q00

decimal

Counts 0–9 then resets. Detects 1010 (10) via NAND on Q3,Q1.

MOD-5 Counter

MOD-5

Q20

Q10

Q00

decimal

Counts 0–4 then resets. Detects 0101 (5) via NAND on Q2,Q0.

MOD-7 Counter

MOD-7

Q20

Q10

Q00

decimal

Counts 0–6 then resets. Detects 0111 (7) via NAND on Q2,Q1,Q0.

MOD-11 Counter

MOD-11

Q30

Q20

Q10

Q00

decimal

Counts 0–10 then resets. Detects 1011 (11) via NAND on Q3,Q1,Q0.

Synchronous Counters

Definition

A synchronous counter is one where all flip-flops share a common clock signal and change states simultaneously (within one propagation delay). There is no ripple — every FF responds to the same clock edge. The J and K inputs are controlled by combinational logic to produce the correct count sequence.

Ripple (Async) Counter

✓Simple circuit — fewer connections
✓Each FF clocks the next naturally
✗Propagation delay accumulates
✗Glitches during transitions
✗Maximum frequency limited by n × tpd

Synchronous Counter

✓All FFs clocked simultaneously
✓No cumulative delay — much faster
✓No glitches at intermediate states
✓Maximum frequency = 1/tpd (just one FF delay)
✗More complex J/K input logic required

Feature	Asynchronous (Ripple)	Synchronous
Clock	Each FF clocked by previous Q'	All FFs share one common CLK
Speed	n × tpd (slow for large n)	1 × tpd (fast!)
Glitches	Yes — intermediate states	No — simultaneous transition
Logic needed	Simple (just connect outputs)	AND gate chain for J/K inputs
Modular design	Easy to extend	Needs redesign for each MOD
ICs	7493 (4-bit ripple)	74163 (4-bit sync), 74192 (BCD sync)

2-bit Synchronous Up Counter

Uses 2 JK flip-flops. Both clocked simultaneously. FF0 always toggles (J0=K0=1). FF1 toggles only when Q0=1 (J1=K1=Q0).

Q1 Q0	Q1⁺ Q0⁺	J1 K1	J0 K0
00	01	0 X	1 X
01	10	1 X	X 1
10	11	X 0	1 X
11	00	X 1	X 1

J0 = K0 (always toggle)

J0 = K0 = 1

J1 = K1 (toggle when Q0=1)

J1 = K1 = Q0

2-bit Synchronous MOD-4 Counter

Q10

Q00

decimal

4-bit Synchronous Up Counter (MOD-16)

Pattern: each FF toggles when all lower-order FFs are 1. This creates an AND gate "carry chain" — each higher FF needs a wider AND gate.

Fig 5.3 — All FFs share a common CLK; J/K inputs driven by AND gate carry chain

Flip-Flop	J = K =	Meaning
FF0 (Q0 — LSB)	1	Always toggles on every clock
FF1 (Q1)	Q0	Toggles when Q0 = 1
FF2 (Q2)	Q1 · Q0	Toggles when Q1 = 1 AND Q0 = 1
FF3 (Q3 — MSB)	Q2 · Q1 · Q0	Toggles when Q2=Q1=Q0=1 (count = 7 → 8)

4-bit Synchronous MOD-16 Counter

Q30

Q20

Q10

Q00

decimal

Synchronous Counter Design Procedure

Click each step to expand the full explanation.

Worked Example: Synchronous MOD-6 Counter

State sequence: 000 → 001 → 010 → 011 → 100 → 101 → 000

Unused states: 110, 111 → all J,K entries = X (don't care)

Q2 Q1 Q0	Q2⁺ Q1⁺ Q0⁺	J2 K2	J1 K1	J0 K0
000	001	0 X	0 X	1 X
001	010	0 X	1 X	X 1
010	011	0 X	X 0	1 X
011	100	1 X	X 1	X 1
100	101	X 0	0 X	1 X
101	000	X 1	0 X	X 1
110	X X X	X X	X X	X X
111	X X X	X X	X X	X X

K-map results (3 variables: Q2, Q1, Q0):

J0 = 1 K0 = 1 (always toggle)

J1 = Q2'Q0 K1 = Q0

J2 = Q1Q0 K2 = Q0

Simplified JK input equations for all three flip-flops

3-bit Synchronous MOD-6 Counter

Q20

Q10

Q00

decimal

Up/Down Synchronous Counter

An up/down synchronous counter adds a direction control input UP/DOWN (M). When M=1: counts up. When M=0: counts down. The J/K equations use M to select the appropriate toggle conditions.

JK equations for up/down 4-bit counter

FF0:J0 = K0 = 1

FF0 always toggles regardless of direction

FF1:J1 = K1 = M·Q0 + M'·Q0'

M=1 (up): toggles when Q0=1. M=0 (down): toggles when Q0=0

FF2:J2 = K2 = M·Q1·Q0 + M'·Q1'·Q0'

Up: toggle when Q1=Q0=1. Down: toggle when Q1=Q0=0

FF3:J3 = K3 = M·Q2·Q1·Q0 + M'·Q2'·Q1'·Q0'

Up: toggle when Q2=Q1=Q0=1. Down: when all lower=0

4-bit Synchronous MOD-16 Counter

Q30

Q20

Q10

Q00

decimal

Special Counters

BCD Counter (Decade Counter / MOD-10)

A BCD (Binary-Coded Decimal) counter counts from 0 to 9 in BCD (4-bit binary), then resets to 0. Also called a decade counteror MOD-10 counter. It has 10 states and produces a BCD output.

Count	Q3	Q2	Q1	Q0	Note
0	0	0	0	0	.
1	0	0	0	1	.
2	0	0	1	0	.
3	0	0	1	1	.
4	0	1	0	0	.
5	0	1	0	1	.
6	0	1	1	0	.
7	0	1	1	1	.
8	1	0	0	0	.
9	1	0	0	1	.
10	1	0	1	0	← NAND detects → Reset to 0

Reset condition

NAND inputs: Q3 · Q1 (binary 10 = 1010)

Why BCD counters matter

Digital clocks use multiple BCD counters (seconds, minutes, hours)
Calculators and 7-segment displays work in decimal — BCD is natural
Each BCD digit requires one decade counter + one 7-segment decoder
IC 7490 is a standard BCD counter IC

Ring Counter

A ring counter is a shift register with the output of the last flip-flop connected back to the input of the first (direct feedback). Only one FF is HIGH at any time — the single '1' circulates around the ring.

4-bit Ring Counter States

Clock	Q0	Q1	Q2	Q3
0 (init)	1	0	0	0
1	0	1	0	0
2	0	0	1	0
3	0	0	0	1
4 (repeat)	1	0	0	0

Key properties:

n FFs → n states → MOD-n counter
Only one FF is HIGH at any time (one-hot encoding)
No decoder needed for state identification
Load initial state: 1000...0 using PRESET
Feedback: Q(n-1) → D(0) (or J0=Q(n-1), K0=Q(n-1)')

Ring Counter (4-bit)

MOD-4 • 4 states

Current state:

Q01

Q10

Q20

Q30

Cycle: 0 of 4

→

1000

Feedback connection

D₀ = Q(n-1) or J₀ = Q(n-1), K₀ = Q(n-1)'

Johnson Counter (Twisted Ring Counter)

A Johnson counter (also called switch-tail or twisted-ring counter) connects the complement (Q') of the last FF back to the input of the first FF. This twist doubles the number of states compared to a ring counter: n FFs → 2n states.

4-bit Johnson Counter — 8 States

Clock	Q0	Q1	Q2	Q3
0 (init)	0	0	0	0
1	1	0	0	0
2	1	1	0	0
3	1	1	1	0
4	1	1	1	1
5	0	1	1	1
6	0	0	1	1
7	0	0	0	1
8 (repeat)	0	0	0	0

Feedback (twisted)

D₀ = Q(n-1)' (complement feedback)

Johnson Counter (4-bit)

MOD-8 • 8 states

Current state:

Q00

Q10

Q20

Q30

Cycle: 0 of 8

→

0000

Ring vs Johnson Counter — Comparison

Feature	Ring Counter	Johnson Counter
Feedback	Q(n-1) → D₀ (direct)	Q'(n-1) → D₀ (complement)
States for n FFs	n states	2n states
Initial state	1000...0 (preloaded)	0000...0 (natural start)
One-hot?	Yes — exactly one 1 at a time	No — varies
Decoder needed	No — each FF = one state	Simple 2-input AND gate per state
4 FFs → states	4 states (MOD-4)	8 states (MOD-8)
Glitches	None (only 1 bit changes)	None (only 1 bit changes)
Pattern	1000, 0100, 0010, 0001	0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001

Memory trick: "Johnson has more states — it's richer/more interesting — because it uses the complement (twist)." Ring = n states. Johnson = 2n states. Always exactly twice as many.

Gray Code Counter

A Gray code counter counts in Gray code sequence — at each step, only one bit changes. This eliminates the glitch problem of binary counters where multiple bits change simultaneously (e.g., 0111 → 1000 — four bits change at once in binary).

Count	Binary	Gray Code	Changes
0	0000	0000	—
1	0001	0001	1 bit ✓
2	0010	0011	1 bit ✓
3	0011	0010	1 bit ✓
4	0100	0110	1 bit ✓
5	0101	0111	1 bit ✓
6	0110	0101	1 bit ✓
7	0111	0100	1 bit ✓
8	1000	1100	1 bit ✓
9	1001	1101	1 bit ✓
10	1010	1111	1 bit ✓
11	1011	1110	1 bit ✓
12	1100	1010	1 bit ✓
13	1101	1011	1 bit ✓
14	1110	1001	1 bit ✓
15	1111	1000	1 bit ✓

Why Gray code eliminates glitches

In binary counting from 7 to 8: 0111 → 1000. All 4 bits change. If bits change at slightly different times due to propagation delays, we see spurious states: 0110, 0100, 0000 before settling at 1000.

In Gray code 7→8: 0100 → 1100. Only ONE bit changes. There is no intermediate incorrect state.

Binary → Gray conversion

G₃ = B₃, G₂ = B₃ ⊕ B₂, G₁ = B₂ ⊕ B₁, G₀ = B₁ ⊕ B₀

Gᵢ = Bᵢ ⊕ B(i+1) [MSB pass-through]

Applications

Shaft encoders (position sensors)
Karnaugh maps (Gray code ordering)
Error correction in digital communications
ADC (analog-to-digital) converters

Shift Registers — Detailed Study

Shift Registers — In Depth

A shift register is a cascade of flip-flops sharing the same clock, where the output of each FF feeds the input of the next. Data is moved (shifted) one position per clock cycle. The 4 types differ in how data enters and exits.

▶▶

SISO

Serial In Serial Out

In: Serial

Out: Serial

Load: n CLK | Read: n CLK

▶⊞

SIPO

Serial In Parallel Out

In: Serial

Out: Parallel

Load: n CLK | Read: 1 CLK

⊞▶

PISO

Parallel In Serial Out

In: Parallel

Out: Serial

Load: 1 CLK | Read: n CLK

⊞⊞

PIPO

Parallel In Parallel Out

In: Parallel

Out: Parallel

Load: 1 CLK | Read: 1 CLK

SISO — Serial-In, Serial-Out

Each bit enters the first FF serially (one per clock). The same bit exits the last FF after n clock cycles. Acts as an n-clock-cycle delay line.

4-bit SISO: Input 1011 (MSB first)

CLK00000initial

CLK1 (in=1)1000bit 1 entered

CLK2 (in=0)0100bit 0 entered

CLK3 (in=1)1010bit 1 entered

CLK4 (in=1)1101bit 1 entered

CLK50110Serial out = 1 (MSB exits)

CLK60011Serial out = 1

CLK70001Serial out = 0

CLK80000Serial out = 1 (LSB exits)

Fig 5.4 — Serial-In Serial-Out: data enters one bit per clock and exits after n clocks

Circuit Description

D₀ input:Connected to serial data input line

D₁ = Q₀:Output of FF0 feeds input of FF1

D₂ = Q₁:Output of FF1 feeds input of FF2

D₃ = Q₂:Output of FF2 feeds input of FF3

Serial output:Q₃ — MSB exits after 4 clocks

Transfer function

Output = Input delayed by n clock cycles

Applications

Time delay circuits
Pipeline stage buffers
Echo/reverb in audio DSP

SIPO — Serial-In, Parallel-Out

Same circuit as SISO — all 4 FF outputs (Q0–Q3) are simultaneously available as parallel outputs. After n clock cycles, all n bits are ready at once. This is serial-to-parallel conversion.

Fig 5.5 — Serial-In Parallel-Out: after n clocks, all n bits available simultaneously

Serial to Parallel: 1011 input

After 4 clock cycles:

Q0=1, Q1=1, Q2=0, Q3=1

(data is reversed in the register — LSB is at Q0)

Applications

UART receiver (serial data → parallel byte)
SPI/I2C data reception
Keypad/encoder input conversion
Serial-to-parallel interface chips (74164)

PISO — Parallel-In, Serial-Out

PISO has two phases: Load (all bits loaded in parallel in 1 clock) and Shift (bits shifted out serially, one per clock). Controlled by a LOAD/SHIFT select signal.

Operation: Load 1011, then shift out

LOAD pulse1011all 4 bits loaded at once

CLK1 (shift)0101MSB (1) exits as serial out

CLK2 (shift)0010next bit (0) exits

CLK3 (shift)0001next bit (1) exits

CLK4 (shift)0000last bit (1) exits

Fig 5.6 — Parallel-In Serial-Out: load all bits at once, then shift out one per clock

2:1 MUX at each FF input

Each FF has a 2:1 MUX controlling its D input:

When LOAD=1: D = parallel data input

When LOAD=0: D = Q of previous FF (shift)

Applications

UART transmitter (parallel byte → serial)
SPI/I2C data transmission
Parallel-to-serial interface (74165)
Microcontroller SPI hardware

PIPO — Parallel-In, Parallel-Out

The simplest and fastest mode. All n bits are loaded simultaneously and all n outputs are available simultaneously — a 1-clock store and retrieve. This is the structure of all CPU registers (AX, BX, SP, etc.).

PIPO operation

• Apply data to D₀, D₁, D₂, D₃ (parallel inputs)

• On clock edge: all bits captured simultaneously

• Q₀, Q₁, Q₂, Q₃ all available immediately after

• Total operation: 1 clock cycle

CPU Register Applications

AX, BX, CX, DXGeneral-purpose data registers

SP (Stack Pointer)Stores current stack address

PC (Program Counter)Holds address of next instruction

IR (Instruction Register)Holds current executing instruction

MAR, MBRMemory address and buffer registers

Universal Shift Register (Bidirectional)

A universal shift register supports all four modes plus both left and right shift directions — controlled by select bits S₁ and S₀. The IC 74194 is the standard universal shift register.

S₁	S₀	Mode	Operation
0	0	Hold	No change — present state maintained regardless of clock
0	1	Shift Right	DSR → Q0 → Q1 → Q2 → Q3 (data shifts right, serial right input used)
1	0	Shift Left	DSL → Q3 → Q2 → Q1 → Q0 (data shifts left, serial left input used)
1	1	Parallel Load	All 4 data inputs (A,B,C,D) loaded simultaneously into Q0-Q3

IC 74194 Pin Summary

CLK:Common clock (positive-edge triggered)

CLR (active low):Asynchronous clear — immediate reset to 0

S₁, S₀:Mode select: 00=Hold, 01=Right, 10=Left, 11=Load

A, B, C, D:Parallel data inputs

DSR:Serial right input (used in shift-right mode)

DSL:Serial left input (used in shift-left mode)

QA-QD:Parallel outputs

Detailed Shift Register Demo

→

Q00

Q10

Q20

Q30

Serial In:

📌 Output: Q0,Q1,Q2,Q3 available simultaneously

Shift Register Applications

Serial Communication (UART)

PISO in transmitter converts parallel byte → serial bitstream. SIPO in receiver rebuilds serial stream → parallel byte. Used in RS-232, USB, I2C, SPI.

Ring Counters & Sequence Generators

A SISO with Q(n-1) fed back to input creates ring counter. With Q'(n-1) feedback creates Johnson counter. Used for timing sequences, LED chasers.

Pseudo-Random Number Generators (LFSR)

Linear Feedback Shift Register: specific taps XOR'd and fed back. Generates maximal-length pseudo-random sequence. Used in cryptography, BIST (built-in self-test).

Digital Signal Processing

SISO registers create sample delays. FIR filter taps access delayed samples. A delay line of n samples = n-stage SISO shift register clocked at sample rate.

Memory Address Generation

PIPO registers in memory controllers hold current address. Shift registers in DMA controllers advance through memory addresses sequentially.

Arithmetic Operations

Left shift = multiply by 2. Right shift = divide by 2. Bidirectional register can multiply/divide in one clock cycle. CPU ALUs use this for fast arithmetic.

Mode	Input	Output	CLKs to load	CLKs to read	Use case	IC
SISO	Serial	Serial	n	n	Delay line	—
SIPO	Serial	Parallel	n	1	Serial→Parallel	74164
PISO	Parallel	Serial	1	n	Parallel→Serial	74165
PIPO	Parallel	Parallel	1	1	CPU registers	74173
Bidir	Both	Both	1 or n	1 or n	Arithmetic shift	74194

Counter & Register Applications

Frequency Division

Every T flip-flop (or JK with J=K=1) divides its input frequency by 2. Chaining n FFs gives a divide-by-2ⁿ frequency divider. This is one of the most important applications of counters in digital systems.

Divide-by-N using MOD-N counter

A MOD-N ripple counter produces an output at its MSB that completes one cycle every N input clock cycles.

MOD-2: ÷2 (1 FF)

MOD-4: ÷4 (2 FFs)

MOD-10: ÷10 (4 FFs + feedback)

MOD-60: ÷60 (can use MOD-6 × MOD-10 in cascade)

Real-world examples

32,768 Hz crystal oscillator → ÷32768 → 1 Hz for digital watch
CPU: 3 GHz PLL output ÷ various ratios → memory, USB, PCIe clocks
Television: frequency dividers derive horizontal and vertical sync from master clock
DTMF tone generation: divider chains produce precise audio frequencies

Sequence Generators

Counters and shift registers can generate any desired sequence of binary patterns. These sequences are used to control timing, test circuits, generate waveforms, and drive displays.

Sequence Generator

Single 1 moves across — ring counter pattern

●

Step 0

Ring Counter

n FFs → n states. One-hot output (single 1 circulates). No decode logic needed. Used for LED chasers, control state machines.

Johnson Counter

n FFs → 2n states. Glitch-free output. Used in decade counting with simple 2-input gate decoding.

LFSR

Linear Feedback Shift Register. XOR taps on specific stages generate pseudo-random sequence. Maximum length = 2ⁿ-1. Used in crypto, testing.

Digital Timers & Clocks

A digital clock chains multiple MOD-N counters. Seconds use MOD-60, minutes use MOD-60, hours use MOD-12 or MOD-24. Each counter's carry-out (when it resets to 0) clocks the next counter.

Digital Clock — Counter Chain

00:00:00

● Hours (MOD-24)

● Minutes (MOD-60)

● Seconds (MOD-60)

Running at 10× speed for demo

Complete Digital Clock Architecture

Crystal: 32,768 Hz

÷32768 counter → 1 Hz pulse (seconds tick)

MOD-10 (units of seconds) → MOD-6 (tens of seconds) → carry → minutes

MOD-10 (units of minutes) → MOD-6 (tens of minutes) → carry → hours

MOD-10 (units of hours) → MOD-3 (tens of hours, for 24h) or MOD-2 (for 12h)

The carry-out of each counter is used as the clock input for the next, creating a cascaded timer chain.

Practice & Self-Assessment

Quick Recall

TU BCA Exam-Style Questions

6 marks

Draw a 4-bit ripple counter and explain its operation with a timing diagram.

8 marks

Design a synchronous MOD-6 counter using JK flip-flops.

4 marks

What is a ring counter? Draw a 4-bit ring counter and write its state sequence.

4 marks

Differentiate between ring counter and Johnson counter in a table. Give state count for n=4 FFs.

6 marks

Explain the four types of shift registers with their applications.

Mini-Test (8 Questions)

Q1.In an asynchronous (ripple) counter, what clocks each flip-flop after the first?

Q2.A 4-bit ripple counter has a MOD of:

Q3.What is the main advantage of a synchronous counter over a ripple counter?

Q4.To build a MOD-10 counter using ripple design, which bits are detected to reset?

Q5.A 4-bit ring counter has how many states?

Q6.A 4-bit Johnson counter has how many valid states?

Q7.Which shift register mode is used for serial-to-parallel conversion?

Q8.What select combination in a 74194 universal shift register causes parallel load?

How to Remember Unit 5

Memory Tricks for Unit 5

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Ripple = Water ripples outward

In a ripple counter, the clock signal is like a stone thrown in water — it starts at FF0 and 'ripples' outward through FF1, FF2, FF3. Each ring of ripples is delayed — that's the propagation delay.

CLK → FF0 (immediate) → FF1 (1×tpd) → FF2 (2×tpd) → FF3 (3×tpd)

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MOD-N: Binary of N → NAND inputs

To build a ripple MOD-N counter, write N in binary. The 1-bits in that binary number are your NAND gate inputs. Simple! MOD-10 = 1010 → NAND needs Q3 and Q1.

MOD-5 = 0101 → NAND(Q2,Q0) | MOD-7 = 0111 → NAND(Q2,Q1,Q0)

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Sync = Simultaneous S-S-S

Synchronous starts with 'S' — Simultaneous, Stable, Swift. All FFs change at the same moment. Maximum delay = just 1 FF, not n FFs. The price: AND gate chain for J/K inputs.

4-bit sync: J3=K3=Q2·Q1·Q0, J2=K2=Q1·Q0, J1=K1=Q0, J0=K0=1

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Ring = n states, Johnson = 2n states

Ring counter keeps its shape — n FFs, n states. Johnson counter twists the ring (uses complement feedback), which DOUBLES the states. 'Johnson is bigger — 2×.'

4 FFs: Ring = 4 states | Johnson = 8 states | Always exactly 2×

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SIPO/PISO: Think about the SLOW side

The SERIAL side is always SLOW (n clocks). The PARALLEL side is always FAST (1 clock). So: SIPO = slow in, fast out (good for receiving). PISO = fast in, slow out (good for transmitting).

SIPO: n CLKs to receive → 1 CLK to read all | PISO: 1 CLK to load → n CLKs to transmit

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Ring counter needs PRESET, Johnson needs RESET

Ring counter must start with exactly one '1' set (e.g., 1000). You need to PRESET it. Johnson counter starts from all zeros (0000) naturally — just RESET it. This is a common exam trick question.

Ring: initial = 1000 (PRESET) | Johnson: initial = 0000 (RESET)

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Frequency divider: each FF = ÷2

Think of each FF as a 'halver'. 1 FF = ÷2. 2 FFs = ÷4. 3 FFs = ÷8. 4 FFs = ÷16. Formula: n FFs → divide by 2ⁿ. A 4-bit counter at 1 MHz → Q3 output at 62.5 kHz.

n FFs → output freq = input freq / 2ⁿ

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74194 modes: HOLD-RIGHT-LEFT-LOAD

74194 select bits S1S0: 00=Hold, 01=Right shift, 10=Left shift, 11=Load parallel. Memory trick: 'H-R-L-L' or count up from 0 → Hold, Right, Left, Load.

S1S0: 00→Hold | 01→Right | 10→Left | 11→Load

Counter Types — Master Cheat Sheet

Counter	MOD	Clock method	Delay	Glitches	Design	IC
Ripple (Async)	2ⁿ	Q' of previous FF	n × tpd	Yes	Simple	7493
Ripple MOD-N	N	Q' + NAND reset	n × tpd	Yes	Add NAND gate	7490 (MOD-10)
Synchronous	2ⁿ	All share 1 CLK	1 × tpd	No	AND gate chain	74163
BCD/Decade	10	Q' + reset at 10	n × tpd	Yes	NAND(Q3,Q1)	7490
Ring	n	Shift register	1 × tpd	No	Direct feedback	—
Johnson	2n	Shift register	1 × tpd	No	Complement feedback	—
Gray Code	2ⁿ	Binary→Gray logic	1 × tpd	No	XOR chain	—

MOD-N Counter Quick Reference

MOD-5

Binary: 0101

NAND: Q2,Q0

FFs: 3

MOD-6

Binary: 0110

NAND: Q2,Q1

FFs: 3

MOD-7

Binary: 0111

NAND: Q2,Q1,Q0

FFs: 3

MOD-8

Binary: 1000

NAND: Q3 only (natural!)

FFs: 3 ← 2³

MOD-10

Binary: 1010

NAND: Q3,Q1

FFs: 4

MOD-11

Binary: 1011

NAND: Q3,Q1,Q0

FFs: 4

MOD-12

Binary: 1100

NAND: Q3,Q2

FFs: 4

MOD-16

Binary: 10000

NAND: natural (4 FFs)

FFs: 4 ← 2⁴

Register Types — The Grid to Memorize

PARALLEL OUT

SERIAL OUT

PARALLEL IN

PIPO

1 CLK in, 1 CLK out

CPU registers

PISO

1 CLK in, n CLKs out

Parallel→Serial (TX)

SERIAL IN

SIPO

n CLKs in, 1 CLK out

Serial→Parallel (RX)

SISO

n CLKs in, n CLKs out

Delay line

Rule: SERIAL side = n CLKs. PARALLEL side = 1 CLK. Simple.

Quick Revision by Section

Exam Checklist — Unit 5

1Draw and explain 4-bit ripple counter circuit and timing diagram

2Explain propagation delay problem in asynchronous counters

3Design MOD-5, MOD-7, MOD-10, MOD-11 ripple counters (NAND method)

4Compare synchronous and asynchronous counters in a table

5Derive JK input equations for 4-bit synchronous up counter

6Design a synchronous MOD-6 counter using JK flip-flops (full K-map)

7Draw up/down synchronous counter and write its JK equations

8Draw and explain ring counter — circuit, state sequence, properties

9Draw and explain Johnson counter — circuit, state sequence, state count

10Compare ring and Johnson counters in a table

11Explain Gray code counter and why it is glitch-free

12Explain SISO, SIPO, PISO, PIPO with circuit and one application each

13Describe bidirectional shift register (74194) and its 4 modes

14Explain how a counter acts as a frequency divider with examples

15Describe digital clock architecture using cascaded MOD-N counters

TU BCA Most-Asked Unit 5 Topics: 4-bit ripple counter with timing diagram (asked almost every year), ring/Johnson counter comparison, MOD-10 counter design, and shift register types with applications. Master these four and you cover 90% of Unit 5 marks.